This application claims priority to Korean Patent Application No. 2002-17090, filed on Mar. 28, 2002, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates, generally, to semiconductor devices and methods of fabricating the same. More specifically, the present invention is directed to nonvolatile memory cells having a split gate structure and methods of fabricating nonvolatile memory cells having a split gate structure.
2. Discussion of Related Art
Semiconductor memory devices for storing data can be typically categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supply is interrupted, and nonvolatile memory devices retain their stored data even when their power supply is interrupted. Accordingly, the nonvolatile memory devices have been widely used in memory cards, mobile telecommunication systems or the like.
The nonvolatile memory devices may have either stacked gate structural cells or split gate structural cells. The split gate structural cells require less power for program operation or erase operation then stacked gate structural cells.
FIG. 1 is a top plan view of a conventional split gate structural cell. FIGS. 2A, 3, 4, 5A, and 6A are cross-sectional views taken along the line Ixe2x80x94I of FIG. 1, and FIGS. 3B, 5B, and 6B are cross-sectional views taken along the line IIxe2x80x94II of FIG. 1.
Referring to FIGS. 1, 2A, and 2B, a tunnel oxide layer 3 and a floating gate layer 5 are sequentially formed on a semiconductor substrate 1. The floating gate layer 5 is formed of a doped polysilicon layer. The floating gate layer 5, the tunnel oxide layer 3, and the semiconductor substrate 1 are patterned to form a trench region defining an active region 7a at a predetermined region of the semiconductor substrate 1. As a result, the active region 7a is covered with the tunnel oxide layer 3 and the floating gate layer 5. A nitride layer pattern 9 is formed on the semiconductor substrate having the device isolation layer 7. The nitride layer pattern 9 has an opening 9a crossing the active region.
Referring to FIGS. 1 and 3, oxide layer spacers 11 are formed on sidewalls of the opening 9a. The floating gate layer 5 exposed in the opening 9a is etched using the oxide layer spacers 11 and the nitride layer pattern 9 as etch masks, to expose the tunnel oxide layer 3 formed on the active region 7a. Impurity ions are then selectively implanted into a surface of the semiconductor substrate under the exposed tunnel oxide layer 3, thereby forming a source region 13.
Referring to FIGS. 1 and 4, the semiconductor substrate having the source region 13 is thermally oxidized to form a sidewall oxide layer on sidewalls of the patterned floating gate layer 5. The sidewall oxide layer (not shown) and the tunnel oxide layer 3 are successively etched using an anisotropic etch process to expose the source region 13 and to simultaneously leave a sidewall oxide layer pattern 15 covering the sidewall of the patterned floating gate layer 5. A doped polysilicon layer is formed on an entire surface of the semiconductor substrate, the sidewall oxide layer pattern 15, and filling the void left from the anisotropic etch. The doped polysilicon layer is etched back until a top surface of the nitride layer pattern 9 is exposed, thereby forming a common source line 17 crossing the active region 7a on the exposed source region 13.
Referring to FIGS. 1, 5A, and 5B, the exposed nitride layer pattern 9, as shown in FIG. 4, is selectively removed to expose the floating gate layer 5 thereunder. Thereafter, the exposed floating gate layer 5 and the tunnel oxide layer 3 are successively etched using the spacers 11 as etch masks, to expose the active region. As a result, as illustrated in FIG. 5A, floating gates 5a are formed between the spacers 11 and the active region 7a. Here, in the event that the floating gate layer 5 and the common source line 17 are formed of a polysilicon layer, the common source line 17 may be also etched while etching the floating gate layer 5. Therefore, a thickness of the floating gate layer 5 should be reduced in order to prevent the common source line 17 from being over-etched.
The semiconductor substrate having the floating gates 5a is thermally oxidized to form a gate oxide layer 19 on the exposed active region. The common source line 17 and the floating gates 5a are also thermally oxidized during formation of the gate oxide layer 19. Thus, the gate oxide layer 19 is formed substantially even with the top surface of the floating gates 5a. Alternatively, the gate oxide layer 19 may be formed substantially even with the top surface of the common source line 17. A gate conductive layer 21 is formed on an entire surface of the semiconductor substrate where the gate oxide layer 19 is formed.
Referring to FIGS. 1, 6A, and 6B, the gate conductive layer 21 is anisotropically etched to form gate electrodes 21a on the vertical sidewalls of the spacers 11 and the top surface of the gate oxide layer 19. The gate electrodes 21a, as illustrated in FIG. 1, cross over the active region and act as word lines. Using the gate electrodes 21a, the spacers 11, and the common source line 17 as ion implantation masks, impurity ions are implanted into the active region to form drain regions 23. An interlayer dielectric layer (ILD) 25 is formed on an entire surface of the semiconductor substrate having the drain regions 23. The ILD 25 is patterned to form bit line contact holes 27 exposing the drain regions 23. Next, a bit line 29 is formed to cover the bit line contact holes 27, which are parallel with the active region.
The foregoing conventional nonvolatile memory cell is programmed by applying a ground voltage to the bit line 29, applying a program voltage to the common source line 17, and applying a voltage higher than a threshold voltage to the gate electrode 21a. In more detail, if a program voltage is applied to the common source line 17, an inversion layer, e.g., a first channel is formed at a surface of the semiconductor substrate 1 under the floating gate 5a. This is because a program voltage applied to the common source line 17 induces a sufficient voltage for forming the first channel to the floating gate 5a. Also, a second channel is formed at the surface of the semiconductor substrate I under the gate electrode 21a. Thus, a strong lateral electric field is formed between the first and second channels, and hot electrons are generated by the lateral electric field.
The hot electrons are injected into the floating gate 5a through the tunnel oxide layer 3. This operation is performed due to a vertical electric field, which is built by a voltage induced to the floating gate 5a. Here, the vertical electric field should be increased in order to improve program efficiency. The vertical electric field is proportional to a coupling ratio of the memory cell, and the coupling ratio has a direct relationship to an overlapped area between the common source line 17 and the floating gate 5a and/or an overlapped area between the source region 13 and the floating gate 5a. Thus, it is required to increase a lateral diffusion of the source region 13 or increase a thickness of the floating gate 5a in order to improve the program efficiency. However, when the thickness of the floating gate 5a is increased, as illustrated in FIG. 5A, the common source line 17 may be over-etched. In addition, if a lateral diffusion of the source region 13 is increased, a punch through phenomenon may occur during a read mode of the nonvolatile memory cell.
It is therefore a feature of the present invention to provide nonvolatile memory devices having a split gate structure and a spacer-shaped floating gate formed in a trench region as well as a common source line overlapped with a sidewall of the spacer-shaped floating gate.
It is another feature of the present invention to provide methods of fabricating nonvolatile memory cells, which can maximize a coupling ratio regardless of a junction depth of a source region and a thickness of a floating gate.
One aspect of the present invention provides nonvolatile memory cells having a split gate structure. The nonvolatile memory cell comprises a device isolation layer formed at a predetermined region of a semiconductor substrate to define an active region as well as a cell trench region formed in a portion of the active region.
It is preferable that the width of the cell trench region is identical to that of the active region. The cell trench region includes a pair of first sidewalls that face each other, a pair of second sidewalls that face each other, and a bottom surface. The first sidewalls are parallel to a direction that crosses the active region, and the second sidewalls are parallel to the active region.
Consequently, the second sidewalls may correspond to sidewalls of the device isolation layer. The first sidewalls are covered with insulated floating gates. A source region is disposed at the bottom surface of the cell trench region. A common source line is disposed in the cell trench region between the insulated floating gates. The common source line is insulated from the floating gates and electrically connected to the source region. Also, the common source line is extended along the direction that crosses the active region to pass through the device isolation layer.
Insulated word lines, which are parallel with the common source line, are disposed on the active regions that are adjacent to the floating gates. Drain regions are disposed at surfaces of the active regions, which is adjacent to the word lines. The drain regions are located on opposite sides of the common source line and are spaced at a substantially equal distance from the first sidewalls.
Further, an interlayer dielectric layer (ILD) covers the semiconductor substrate having the drain regions, the word lines and the common source line. The drain regions are exposed by bit line contact holes penetrating the ILD. A bit line, which is parallel with the active region, is disposed on the ILD. The bit line is electrically connected to the drain regions through the bit line contact holes.
The floating gates may have a spacer shape. Also, the floating gates are insulated from the first sidewalls and the bottom surface by a tunnel oxide layer. In addition, a sidewall insulation layer is interposed between the floating gates and the common source line.
A gate insulation layer is interposed between the word lines and the active regions. The word lines may be extended to cover the floating gates adjacent to the word lines.
Further, the nonvolatile memory cells may comprise an interlayer dielectric layer formed on an entire surface of the semiconductor substrate having the word lines, the device isolation layer, the common source line, and the drain regions, and a bit line electrically connected to the drain regions through bit line contact holes penetrating predetermined regions of the interlayer dielectric layer, wherein the bit line is disposed to be parallel with the active region.
According to another aspect of the present invention provides methods of fabricating nonvolatile memory cells having a split gate structure. The method comprises forming a device isolation layer at a predetermined region of a semiconductor substrate to define a plurality of parallel active regions. A portion of each of the active regions is selectively etched to form cell trench regions. The respective cell trench regions include a pair of first sidewalls parallel with the direction that crosses the active regions, a pair of second sidewalls parallel with the active regions, and a bottom surface. It is preferable that the width of the cell trench regions is substantially equal to that of the active regions. In this case, the second sidewalls may correspond to sidewalls of the device isolation layer.
Insulated floating gates are formed on the first sidewalls. The device isolation layer between the cell trench regions is selectively etched to form source line trench regions. Source regions are formed at the bottom surfaces of the cell trench regions. In the event that the semiconductor substrate is exposed during formation of the source line trench regions, the source regions may be formed even with the bottom surfaces of the source line trench regions in addition to the bottom surfaces of the cell trench regions. Thus, each of the source regions has a line shape that crosses the active regions.
Alternatively, the source regions may be selectively formed only at the bottom surfaces of the cell trench regions prior to formation of the source line trench regions.
A sidewall insulation layer is selectively formed on sidewalls of the floating gates. Common source lines are formed in the cell trench regions between the floating gates and the source line trench regions. Thus, the common source lines are formed to cross the active regions and electrically connected to the source regions. Also, the common source lines are electrically insulated from the floating gates by the sidewall insulation layer.
Insulated word lines, which are parallel with the common source lines, are formed on the active regions adjacent to the floating gates. The word lines are insulated from the active regions by a gate insulation layer. Drain regions are formed in the active regions adjacent to the word lines. The drain regions are located on opposite sides of the common source lines and are spaced at a substantially equal distance from the first sidewalls.
Also, the methods of fabricating nonvolatile memory cells having a split gate structure according to the present invention may further comprise forming an interlayer dielectric layer on an entire surface of the semiconductor substrate having the drain regions, patterning the interlayer dielectric layer to form bit line contact holes exposing the drain regions, and forming bit lines electrically connected to the drain regions through the bit line contact holes on the interlayer dielectric layer, each of the bit lines is formed over the respective active regions.
In addition, an interlayer dielectric layer (ILD) is formed on substantially an entire surface of the semiconductor substrate having the drain regions. The ILD is patterned to form bit line contact holes exposing the drain regions. Bit lines, which are parallel with the active regions, are formed on the interlayer insulation layer. The bit lines are electrically connected to the drain regions through the bit line contact holes.
Further, the method of fabricating nonvolatile memory cells wherein forming the cell trench regions comprises forming a first photoresist pattern having openings that crosses the active regions on the semiconductor substrate including the device isolation layer, etching the active regions exposed by the openings to a predetermined depth using the first photoresist pattern as an etch mask, and removing the first photoresist pattern. In addition, the predetermined depth of the active regions may be substantially equal to the thickness of the device isolation layer.
Still further, the forming of the insulated floating gates, the source line trench regions, and the source regions comprises thermally oxidizing the semiconductor substrate having the cell trench regions to form a tunnel oxide layer on the first sidewalls and the bottom surfaces, forming spacers covering the first and second sidewalls, forming a second photoresist pattern having openings that crosses the active regions on the semiconductor substrate having the spacers, the openings of the second photoresist pattern expose the spacers formed on the second sidewalls as well as the device isolation layer between the second sidewalls, selectively etching the exposed spacers using the second photoresist pattern as an etch mask to separate the spacers formed on the first sidewalls from each other, etching the exposed device isolation layer using the second photoresist pattern as an etch mask to form source line trench regions between the cell trench regions, implanting impurity ions using the second photoresist pattern as an ion implantation mask to form source regions at the bottom surfaces of the cell trench regions, and removing the second photoresist pattern.
Also, the etching process for forming the source line trench regions is performed until the semiconductor substrate is exposed, the source regions being formed even with the bottom surfaces of the source line trench regions in addition to the bottom surfaces of the cell trench regions to have a line shape which is parallel with the direction that crosses the active region.
The forming of the sidewall insulation layer comprises conformally forming an insulation layer on an entire surface of the semiconductor substrate having the source region, and anisotropically etching the insulation layer to form a sidewall insulation layer on the sidewalls of the floating gates and to expose the source regions.
The forming of the common source lines comprises forming a conductive layer filling the cell trench regions and the source line trench regions on an entire surface of the semiconductor substrate having the sidewall insulation layer, and planarizing the conductive layer until the device isolation layer and the active regions are exposed.
The forming of the insulated word lines comprises forming a gate insulation layer on an entire surface of the semiconductor substrate having the common source line, forming a gate conductive layer on the gate insulation layer, and patterning the gate conductive layer to form word lines covering the active regions adjacent to the floating gates and being parallel with the common source lines.
These foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings, wherein like reference members represent like parts of the invention.